This application claims priority from Korean Patent Application No. 2002-06478, filed on Oct. 23, 2002, the contents of which are incorporated herein by reference in their entirety.
1. Field of the Invention
The present invention relates to the filed of a non-volatile memory device and, more particularly, to a non-volatile memory device to protect a floating gate from charge loss and a method for fabricating the same.
2. Description of the Related Art
In EEPROM (Electrically Erasable and Programmable Read Only Memory) devices, information can be stored by varying the amount of electrical charges within floating gate structures, i.e., altering the threshold voltages of transistors.
The reliability of EEPROM devices mainly depends on their endurance and charge retention characteristics. The endurance characteristic is the ability to maintain the threshold voltage independently of environmental conditions, and the charge retention characteristic is the capability to retain charges in the floating gate. The endurance characteristic may be weakened by the deterioration of the tunnel oxide layer, which is mainly caused by tunneling of charges. The charge retention characteristic may be weakened by charge loss caused by positive mobile ions and also by the defects of the dielectric layer that covers the floating gate. Namely, positive ions (e.g. hydrogen ions) in the dielectric layer covering the floating gate are introduced into the floating gate. The positive ions introduced into the floating gate are coupled to the electrons that are accumulated in the floating gate. Therefore, charge loss occurs and charge retention capability of the non-volatile memory device is deteriorated.
For this reason, positive mobile ion contamination during the fabrication of an EEPROM device must be reduced to a minimum to prevent degradation of charge retention characteristic. In particular, it is required that positive mobile ions (H+, K+, Na+, etc) be prevented from being introduced into the floating gate through the dielectric layer adjacent the floating gate. In this sense, deterioration of charge retention characteristic caused by positive mobile ions near the floating gate is a major problem because the number of charges needed to alter threshold voltage decreases as the device size becomes smaller.
One approach to reduce charge loss of the non-volatile memory device is formation of a barrier layer to prevent hydrogen ions from diffusing into the floating gate is disclosed in U.S. Pat. No. 6,287,916 entitled xe2x80x9cMETHOD FOR FORMING A SEMICONDUCTOR DEVICE USING LPCVD NITRIDE TO PROTECT FLOATING GATE FROM CHARGE LOSSxe2x80x9d. This method comprises a step of depositing a barrier layer after a step of forming a gate. In this invention, hydrogen ions are prevented from being introduced into the floating gate.
On the other hand, as the integration degree of the non-volatile memory device increases, the STI (Shallow Trench Isolation) process is mainly used for device isolation instead of the LOCOS (Local Oxidation of Silicon) process. In the LOCOS process, a field region that defines an active region is formed by thermal oxidation. On the other hand, in the STI process, a field region is formed of Chemical Vapor Deposition (CVD) oxide filling the trench. With respect to the thermal oxide layer, this gap-fill oxide layer contains many positive porous ions. The positive ions contained in the gap-fill oxide layer may be positive ions caused by a CMP (Chemical Mechanical Polishing) or metal contact process. These positive ions can be introduced into the floating gate through the gap-fill oxide layer, thereby deteriorating device characteristics such as charge retention characteristics.
The present invention provides, among other things, a non-volatile memory device that can protect a floating gate from charge loss and a method for fabricating the same.
In the present invention, positive mobile ions can be prevented from penetrating the floating gate through the gap-fill oxide layer. To this end, a gap-fill dielectric layer is implanted with, for example, phosphorous ions to form a getter layer that can trap the positive mobile ions.
According to one embodiment, at least a pair of floating gate lines are formed on a semiconductor substrate. The pair of floating gate lines define a gap therebetween. Next, a portion of the substrate between the floating gate lines is etched to form a trench therein. A gap-fill dielectric layer is formed in the trench and also in the gap between the pair of floating gate lines. The gap-fill dielectric layer is implanted with impurities to form a getter layer that can trap positive mobile ions.
Consequently, the positive mobile ions that may permeate the floating gate through the gap-fill dielectric layer can be trapped in the gap-fill dielectric layer.
Next, a conductive layer is formed on the floating gate lines and on the gap-fill dielectric layer with an inter-gate dielectric disposed therebetween. The conductive layer and the floating gate lines are patterned to form a word line and a floating gate.
According to another embodiment of the present invention, a non-volatile memory device comprises a trench field region formed on a substrate. The trench field region defines an active region. A floating gate is positioned on a portion of the active region, and a word line extends over the floating gate and a portion of the trench field region. A getter layer is formed in the trench field region adjacent the floating gate. The getter layer is implanted with, for example, phosphorous ions.